However, due to limitations of the semiconductor integrated circuit manufacturing process or technology (such as photolithography, etching, or the different package, SMT, IR Reflow and other external factors), those will result in the op amp including non-ideal characteristics in practical operation. Therefore, because of non-ideal factors, the input offset voltage of the op amp will be generated. The input offset voltage will deteriorate the op amp and affect the stability of the overall system in subsequent circuit design.
In conventional art, in order to eliminate the input offset voltage, the wafer test (Chip Circuit Probing) or the final level test is used in One Time Programming (OTP) process for correction, and usually includes an additional external components to achieve the correction. At this point, the chip will affect the input offset voltage again by the external factors so as to worsen the performance of the op amp.
In summary, the effect of the input offset voltage in the op amp because of the process or the physical properties of semiconductors is the problem would like to be solved in the present invention.